The subject invention is directed generally to boundary scan testing, and is directed more particularly to boundary scan testing wherein boundary test patterns are applied in such a manner that the output signals at the outputs of a digital device participating in boundary scan testing transition one output signal at a time.
Boundary scan testing is commonly utilized to test the interconnections between digital devices that comprise a system, where the interconnected devices can include integrated circuits, application specific integrated circuits (ASICs), hybrids, and circuit boards, for example. For boundary scan test capability, a device includes scan circuits that are capable of isolating device input circuits and output circuits from the interior logic of the device and directly accessing such input circuits and output circuits, which allows special interconnection test patterns to be applied and observed without interference from the interior logic functions.
Boundary scan test capability is commonly implemented with boundary scan cells respectively associated with those input circuits and output circuits for which boundary scan testing capability is being provided, with each boundary scan cell containing a scan flip-flop. The scan flip-flops are arranged into a register chain that is capable of operation in serial and parallel modes, so that test patterns can be loaded serially, applied in parallel, and test results can be read out serially.
For testing, special interconnection test patterns are serially loaded into scan flip-flops for device output circuits. After a test pattern is loaded, the output scan cells containing the test pattern are switched to drive their associated output circuits in accordance with the test pattern. Subsequently, the signals observed on input circuits are stored in associated input scan flip-flops. The stored inputs are then serially read out to evaluate the test. A further test pattern can be serially loaded into output scan flip-flops while stored inputs are being serially read out.
Boundary scan test patterns are basically designed to achieve the following:
1. To drive each device output to the high state and to the low state at different times. Proper reception at the appropriate inputs verifies continuity.
2. To drive each device output to the state opposite that of all other outputs, for both the low state and the high state. A short circuit between two or more outputs will be indicated by contention between the shorted drivers.
The paper "INTERCONNECT TESTING WITH BOUNDARY SCAN," Wagner, IEEE Proc. 1987 International Test Conference, pages 52-57, generally describes the application and implementation of boundary scan testing, and test patterns that allow for efficient boundary scan testing.
A consideration with known boundary scan circuitry is that up to half of the device outputs participating in a boundary scan test may change pursuant to application of each test pattern, which often causes problems since devices are often not designed to accommodate a large number of simultaneously switching outputs due to factors including induced power and ground noise. A present approach to the problem of simultaneous switching of a large number of device outputs is to successively test subsets of the device output circuits, wherein each subset maintains the number of simultaneously switching outputs to be no greater than the largest number of simultaneously switching outputs that the device was designed to accommodate in actual operation. By independently exercising subsets of the device outputs, the boundary test pattern set for each device becomes unique to such device, which prevents the use of a single, common test pattern set for all devices. Alternatively, the number of power/ground pins could be increased for device, which is undesirable because of limitations on the number of input circuits and output circuits.